Performance-centric roadmap for building a superconducting quantum computer

TL;DR

This paper proposes a performance-centric roadmap for developing superconducting quantum computers, linking gate fidelity to system size and outlining phases for hardware development to achieve quantum advantage.

Contribution

It introduces a quantitative framework connecting algorithm success rates with hardware targets and defines development phases for scalable quantum computing.

Findings

Identifies four phases of quantum hardware development.

Establishes a link between gate fidelity and system size goals.

Provides a roadmap to achieve quantum advantage with NISQ and error-corrected quantum computers.

Abstract

One of the outstanding challenges in contemporary science and technology is building a quantum computer that is useful in applications. By starting from an estimate of the algorithm success rate, we can explicitly connect gate fidelity to quantum system size targets and define a quantitative roadmap that maximizes performance while avoiding distractions. We identify four distinct phases for quantum hardware and enabling technology development. The aim is to improve performance as we scale and increase the algorithmic complexity the quantum hardware is capable of running, the algorithmic radius, towards a point that sets us up for quantum advantage with deep noisy intermediate-scale quantum computing (NISQ) as well as building a large-scale error-corrected quantum computer (QEC). Our hope is that this document contributes to shaping the discussion about the future of the field.