Power- and Area-Efficient Unary Sorting Architecture Using FSM-Based Unary Number Generator

TL;DR

This paper introduces a low-area, power-efficient unary sorting architecture using an FSM-based unary number generator, significantly reducing costs and energy consumption for hardware sorters in resource-constrained systems.

Contribution

It proposes a novel unary sorting module with a finite-state-machine-based generator that eliminates the need for complex comparators, reducing area and power overhead.

Findings

Achieves up to 82% area reduction

Reduces power consumption by 70%

Demonstrates effectiveness in 45nm technology

Abstract

Sorting is a fundamental operation in computer systems and is widely used in applications such as databases, data analytics, and hardware accelerators. Unary computing has recently emerged as a low-cost and power-efficient paradigm for implementing hardware sorters by eliminating the need for complex arithmetic operations. However, existing comparison-free unary computing-based designs suffer from significant area and power overhead due to costly unary number generators. In this paper, we present a novel ascending-order unary sorting module featuring a finite-state-machine-based unary number generator that significantly reduces implementation costs. By generating right-aligned unary streams using a two-state finite-state machine, our architecture iteratively identifies the minimum input value in each cycle without conventional comparators. Synthesis results in a 45nm technology node demonstrate up to 82% reduction in area and 70% reduction in power consumption compared to state-of-the-art unary designs. The proposed sorter offers a promising solution for energy-constrained and resource-limited hardware systems.