Hardware-Aware Quantum Kernel Design Based on Graph Neural Networks

TL;DR

This paper introduces a hardware-aware, learning-based framework for designing quantum kernels optimized for NISQ devices, improving classification accuracy while respecting hardware constraints.

Contribution

It presents a novel graph neural network approach that predicts kernel performance from hardware-specific quantum circuit representations, enabling automated, efficient kernel design.

Findings

Outperforms existing methods in classification accuracy on benchmark datasets.

Effectively balances hardware constraints with model expressivity under noise.

Demonstrates the potential of deep learning for practical quantum kernel deployment.

Abstract

Quantum kernels hold significant promise for achieving computational advantages in quantum machine learning (QML), yet their effectiveness critically depends on the design of expressive and hardware-compatible feature maps, a challenge that is particularly pronounced on Noisy Intermediate-Scale Quantum (NISQ) devices with limited qubits, gate errors, and restricted connectivity. In this work, we propose a hardware-aware framework for automated quantum kernel design that integrates quantum device characteristics with learning-based evaluation. Specifically, candidate quantum circuits explored within the hardware-aware circuit space are represented as directed acyclic graphs (DAGs) encoding hardware-specific information such as gate operations, qubit interactions, and noise properties, while a dual graph neural network (GNN) predictor is employed to estimate key surrogate metrics, including probability of successful trials (PST) and kernel-target alignment (KTA), enabling efficient and accurate assessment of circuit fidelity and kernel performance to facilitate the identification of task-specific quantum kernels. Furthermore, feature selection is incorporated to reduce input dimensionality and ensure compatibility with near-term devices. Extensive experiments on multiple benchmark datasets, including Credit Card (CC), MNIST-5, and FMNIST-4, demonstrate that our method consistently outperforms existing baselines in classification accuracy, effectively balancing hardware constraints and model expressivity under realistic noise conditions. These results highlight the potential of combining hardware-aware design with deep learning techniques to advance practical quantum kernel methods and facilitate their deployment on near-term quantum hardware.