In-Memory Sorting-Searching with Cayley Tree

TL;DR

This paper introduces an in-memory computing platform using Cayley trees to perform data-intensive tasks like searching, sorting, and max/min calculations efficiently, reducing CPU workload and improving performance.

Contribution

It presents a novel IMC platform based on Cayley trees, with hardware implementations and FPGA validation, advancing in-memory data processing techniques.

Findings

Achieves $\\mathcal{O}(\log n)$ time for searching and max/min in-memory.

In-memory sorting has a worst-case complexity of $\mathcal{O}(n \log n)$.

FPGA implementation demonstrates effectiveness compared to existing designs.

Abstract

This work proposes a computing model to reduce the workload of CPU. It relies on the data intensive computation in memory, where the data reside, and effectively realizes an in-memory computing (IMC) platform. Each memory word, with additional logic, acts as a tiny processing element which forms the node of a Cayley tree. The Cayley tree in turn defines the framework for solving the data intensive computational problems. It finds the solutions for in-memory searching, computing the max (min) in-memory and in-memory sorting while reducing the involvement of CPU. The worst case time complexities of the IMC based solutions for in-memory searching and computing max (min) in-memory are $\mathcal{O}\log{n}$. Such solutions are independent of the order of elements in the list. The worst case time complexity of in-memory sorting, on the other hand, is $\mathcal{O}(n\log{n})$. Two types of hardware implementations of the IMC platform are proposed. One is based on the existing/conventional memory architecture, and the other one is on a newly defined memory architecture. The solutions are further implemented in FPGA platform to prove the effectiveness of the IMC architecture while comparing with the state-of-the art designs.