Comparison of spin-qubit architectures for quantum error-correcting codes

TL;DR

This paper compares surface and Bacon-Shor quantum error-correcting codes using spin qubits in silicon, demonstrating that hybrid encoding improves performance and identifying gate errors as the main limiting factor for scalability.

Contribution

It introduces a detailed comparison of two error-correcting codes with different encoding schemes for spin qubits, highlighting the advantages of hybrid encoding and concrete hardware improvement targets.

Findings

Hybrid encoding outperforms pure Zeeman-qubit implementation.

Gate errors, not memory errors, limit logical error rates.

Logical error rate is primarily affected by 1- and 2-qubit gate errors.

Abstract

We investigate the performance of two quantum error-correcting codes, the surface code and the Bacon-Shor code, for implementation with spin qubits in silicon. In each case, we construct a logical qubit using a planar array of quantum dots, exploring two encoding schemes: one based solely on single-electron Zeeman qubits (Loss-DiVincenzo qubits), and a hybrid approach combining Zeeman and singlet-triplet qubits. For both codes, we evaluate key performance metrics, including logical state preparation fidelity and cycle-level error correction performance, using state-of-the-art experimental parameters. Our results show that the hybrid encoding consistently outperforms the pure Zeeman-qubit implementation. By identifying the dominant error mechanisms that limit quantum error correction performance, our study highlights concrete targets for improving spin qubit hardware and provides a path toward scalable fault-tolerant architectures. In particular, we find that the logical error rate is not limited by memory errors, but rather by gate errors, especially 1- and 2-qubit gate errors.