SparseDPD: A Sparse Neural Network-based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization

TL;DR

SparseDPD introduces a sparsely pruned neural network FPGA accelerator that significantly enhances RF power amplifier linearization efficiency and performance, enabling real-time wireless communication applications.

Contribution

It presents a novel FPGA-based neural network accelerator with unstructured pruning, achieving high linearization performance with low power and computational complexity.

Findings

Achieves ACPR of -59.4 dBc, EVM of -54.0 dBc, NMSE of -48.2 dB.

Operates at 170 MHz on a Xilinx Zynq-7Z010 FPGA.

Uses only 241 mW dynamic power with 74% sparsity in 64 parameters.

Abstract

Digital predistortion (DPD) is crucial for linearizing radio frequency (RF) power amplifiers (PAs), improving signal integrity and efficiency in wireless systems. Neural network (NN)-based DPD methods surpass traditional polynomial models but face computational challenges limiting their practical deployment. This paper introduces SparseDPD, an FPGA accelerator employing a spatially sparse phase-normalized time-delay neural network (PNTDNN), optimized through unstructured pruning to reduce computational load without accuracy loss. Implemented on a Xilinx Zynq-7Z010 FPGA, SparseDPD operates at 170 MHz, achieving exceptional linearization performance (ACPR: -59.4 dBc, EVM: -54.0 dBc, NMSE: -48.2 dB) with only 241 mW dynamic power, using 64 parameters with 74% sparsity. This work demonstrates FPGA-based acceleration, making NN-based DPD practical and efficient for real-time wireless communication applications. Code is publicly available at https://github.com/MannoVersluis/SparseDPD.