DeepRTL2: A Versatile Model for RTL-Related Tasks

TL;DR

DeepRTL2 is a versatile large language model designed to handle both generation and embedding tasks in RTL-related electronic design automation, achieving state-of-the-art results across diverse tasks and streamlining hardware design workflows.

Contribution

DeepRTL2 introduces a unified LLM framework that addresses both generation and embedding tasks in RTL, filling a critical gap in EDA workflows and being the first to do so comprehensively.

Findings

Achieves state-of-the-art performance on multiple RTL tasks

Unifies generation and embedding tasks in a single model

Significantly improves efficiency in RTL code understanding and generation

Abstract

The integration of large language models (LLMs) into electronic design automation (EDA) has significantly advanced the field, offering transformative benefits, particularly in register transfer level (RTL) code generation and understanding. While previous studies have demonstrated the efficacy of fine-tuning LLMs for these generation-based tasks, embedding-based tasks, which are equally critical to EDA workflows, have been largely overlooked. These tasks, including natural language code search, RTL code functionality equivalence checking, and performance prediction, are essential for accelerating and optimizing the hardware design process. To address this gap, we present DeepRTL2, a family of versatile LLMs that unifies both generation- and embedding-based tasks related to RTL. By simultaneously tackling a broad range of tasks, DeepRTL2 represents the first model to provide a comprehensive solution to the diverse challenges in EDA. Through extensive experiments, we show that DeepRTL2 achieves state-of-the-art performance across all evaluated tasks.