SR-NCL: an Area-/Energy-Efficient Resilient NCL Architecture Based on Selective Redundancy

TL;DR

This paper introduces a new resilient NCL architecture that uses selective redundancy to improve energy and area efficiency in asynchronous circuits, specifically for image processing applications.

Contribution

It proposes a novel error-tolerant NCL architecture based on selective redundancy, reducing overhead compared to traditional duplication-based designs.

Findings

Significant reduction in area and energy consumption.

Effective error tolerance in NCL circuits.

Improved suitability for image processing applications.

Abstract

Duplication-based redundancy schemes have proven to be effective in designing fully-resilient Quasi-delay Insensitive (QDI) asynchronous circuits. The complete resiliency, however, is accompanied by significant energy, latency, and area overhead. This paper presents a novel error-tolerant Null Convention Logic (NCL) architecture based on selective redundancy. Results demonstrate the efficacy of the proposed method in terms of area and energy utilization as compared to existing duplication-based NCL designs, targeting an image processing application.