J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor
Benoit Tain, Raphael Millet, Romain Lemaire, Michal Szczepanski, Laurent Alacoque, Emmanuel Pluchart, Sylvain Choisnet, Rohit Prasad, Jerome Chossat, Pascal Pierunek, Pascal Vivet, Sebastien Thuries

TL;DR
J3DAI is a compact DNN-based hardware accelerator integrated into a 3D-stacked CMOS image sensor, enabling efficient edge AI processing with optimized performance, power, and area characteristics.
Contribution
This work introduces J3DAI, a novel tiny DNN accelerator integrated into a 3D-stacked CMOS sensor, with a supporting software framework for efficient edge AI applications.
Findings
Demonstrates high efficiency and versatility in image classification and segmentation tasks.
Achieves significant reductions in memory footprint and computational complexity through post-training quantization.
Showcases potential for real-time, low-latency, energy-efficient AI processing at the edge.
Abstract
This paper presents J3DAI, a tiny deep neural network-based hardware accelerator for a 3-layer 3D-stacked CMOS image sensor featuring an artificial intelligence (AI) chip integrating a Deep Neural Network (DNN)-based accelerator. The DNN accelerator is designed to efficiently perform neural network tasks such as image classification and segmentation. This paper focuses on the digital system of J3DAI, highlighting its Performance-Power-Area (PPA) characteristics and showcasing advanced edge AI capabilities on a CMOS image sensor. To support hardware, we utilized the Aidge comprehensive software framework, which enables the programming of both the host processor and the DNN accelerator. Aidge supports post-training quantization, significantly reducing memory footprint and computational complexity, making it crucial for deploying models on resource-constrained hardware like J3DAI. Our…
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