Toward a Lightweight, Scalable, and Parallel Secure Encryption Engine

TL;DR

This paper introduces SPiME, a novel FPGA-compatible architecture that integrates AES encryption into a scalable, parallel Processing-in-Memory framework, significantly enhancing throughput and efficiency for IoT edge security.

Contribution

The paper presents SPiME, a modular, FPGA-implementable PiM-based encryption architecture that achieves high scalability and throughput with minimal resource utilization.

Findings

Scales beyond 4,000 parallel PiM units.

Achieves over 25 Gbps encryption throughput.

Uses less than 5% FPGA resources on high-end devices.

Abstract

The exponential growth of Internet of Things (IoT) applications has intensified the demand for efficient, high-throughput, and energy-efficient data processing at the edge. Conventional CPU-centric encryption methods suffer from performance bottlenecks and excessive data movement, especially in latency-sensitive and resource-constrained environments. In this paper, we present SPiME, a lightweight, scalable, and FPGA-compatible Secure Processor-in-Memory Encryption architecture that integrates the Advanced Encryption Standard (AES-128) directly into a Processing-in-Memory (PiM) framework. SPiME is designed as a modular array of parallel PiM units, each combining an AES core with a minimal control unit to enable distributed in-place encryption with minimal overhead. The architecture is fully implemented in Verilog and tested on multiple AMD UltraScale and UltraScale+ FPGAs. Evaluation results show that SPiME can scale beyond 4,000 parallel units while maintaining less than 5\% utilization of key FPGA resources on high-end devices. It delivers over 25~Gbps in sustained encryption throughput with predictable, low-latency performance. The design's portability, configurability, and resource efficiency make it a compelling solution for secure edge computing, embedded cryptographic systems, and customizable hardware accelerators.