Reconfigurable Digital RRAM Logic Enables In-Situ Pruning and Learning for Edge AI
Songqi Wang, Yue Zhang, Jia Chen, Xinyuan Zhang, Yi Li, Ning Lin, Yangu He, Jichang Yang, Yingjie Yu, Yi Li, Zhongrui Wang, Xiaojuan Qi, Han Wang

TL;DR
This paper introduces a reconfigurable digital RRAM-based compute-in-memory chip and a dynamic pruning algorithm that together enable efficient, in-memory AI training and inference with reduced energy and hardware overhead, inspired by brain synaptic plasticity.
Contribution
It presents a novel co-designed hardware-software system combining a digital RRAM CIM chip with a real-time pruning algorithm for edge AI.
Findings
Reduces operations by up to 59.94% without accuracy loss.
Achieves 57.26% energy savings over analogue RRAM CIM.
Outperforms NVIDIA RTX 4090 in energy efficiency for edge tasks.
Abstract
The human brain simultaneously optimizes synaptic weights and topology by growing, pruning, and strengthening synapses while performing all computation entirely in memory. In contrast, modern artificial-intelligence systems separate weight optimization from topology optimization and depend on energy-intensive von Neumann architectures. Here, we present a software-hardware co-design that bridges this gap. On the algorithmic side, we introduce a real-time dynamic weight-pruning strategy that monitors weight similarity during training and removes redundancies on the fly, reducing operations by 26.80% on MNIST and 59.94% on ModelNet10 without sacrificing accuracy (91.44% and 77.75%, respectively). On the hardware side, we fabricate a reconfigurable, fully digital compute-in-memory (CIM) chip based on 180 nm one-transistor-one-resistor (1T1R) RRAM arrays. Each array embeds flexible Boolean…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Modular Robots and Swarm Intelligence · Ferroelectric and Negative Capacitance Devices
