Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications

TL;DR

This paper explores integrating FPGA and ASIP accelerators to enhance onboard AI/ML capabilities in space applications, emphasizing device selection and architecture design for future satellite missions.

Contribution

It presents industrial trends, benchmarking results, and architectural designs combining FPGAs and AI accelerators for space-based AI/ML systems.

Findings

FPGAs significantly improve processing power in space applications.

Benchmarking guides optimal device selection for onboard AI.

Architectural designs enable efficient AI/ML deployment in satellites.

Abstract

The success of AI/ML in terrestrial applications and the commercialization of space are now paving the way for the advent of AI/ML in satellites. However, the limited processing power of classical onboard processors drives the community towards extending the use of FPGAs in space with both rad-hard and Commercial-Off-The-Shelf devices. The increased performance of FPGAs can be complemented with VPU or TPU ASIP co-processors to further facilitate high-level AI development and in-flight reconfiguration. Thus, selecting the most suitable devices and designing the most efficient avionics architecture becomes crucial for the success of novel space missions. The current work presents industrial trends, comparative studies with in-house benchmarking, as well as architectural designs utilizing FPGAs and AI accelerators towards enabling AI/ML in future space missions.