Cut Tracing with E-Graphs for Boolean FHE Circuit Synthesis

TL;DR

This paper introduces cut tracing with e-graphs to optimize FHE circuits by balancing multiplicative depth and complexity, significantly reducing homomorphic evaluation runtime.

Contribution

It proposes a novel method combining two existing optimization flows using e-graphs to improve overall FHE circuit performance.

Findings

Up to 40% reduction in homomorphic evaluation runtime.

Effective combination of MC and MD optimization flows.

Demonstrated improvement on benchmark circuits.

Abstract

Fully Homomorphic Encryption (FHE) is a promising privacy-preserving technology enabling secure computation over encrypted data. A major limitation of current FHE schemes is their high runtime overhead. As a result, automatic optimization of circuits describing FHE computation has garnered significant attention in the logic synthesis community. Existing works primarily target the multiplicative depth (MD) and multiplicative complexity (MC) of FHE circuits, corresponding to the total number of multiplications and maximum number of multiplications in a path from primary input to output, respectively. In many FHE schemes, these metrics are the primary contributors to the homomorphic evaluation runtime of a circuit. However, oftentimes they are opposed: reducing either depth or complexity may result in an increase in the other. To our knowledge, existing works have yet to optimize FHE circuits for overall runtime, only considering one metric at a time and thus making significant tradeoffs. In this paper, we use e-graphs to augment existing flows that individually optimize MC and MD, in a technique called cut tracing. We show how cut tracing can effectively combine two state-of-the-art MC and MD reduction flows and balance their weaknesses to minimize runtime. Our preliminary results demonstrate that cut tracing yields up to a 40% improvement in homomorphic evaluation runtime when applied to these two flows.