A Novel Thermal Network Model and Electro-Thermal Coupling Study for NSFETs and CFETs Considering Thermal Crosstalk

TL;DR

This paper introduces a thermal network model that accurately predicts self-heating and thermal crosstalk in NSFETs and CFETs, revealing that CFETs experience more severe thermal issues affecting device and circuit performance.

Contribution

A new thermal network model considering thermal crosstalk is proposed, enabling precise analysis of thermal effects in nanosheet FETs and CFETs, aiding in device optimization.

Findings

CFETs exhibit more severe self-heating and crosstalk than NSFETs.

Thermal effects significantly impact the performance of logic gates and ring oscillators.

The model can guide thermal optimization and design co-optimization strategies.

Abstract

As the technology node continues to shrink, nanosheet field effect transistors (NSFETs) and complementary FETs (CFETs) become valid candidates for the 3nm and sub-nanometre nodes. However, due to the shrinking device size, self-heating and inter-device thermal crosstalk of NSFETs and CFETs become more severe. It is important to accurately calculate the self-heating and thermal crosstalk of devices and to study the electrical and thermal characteristics of logic gates, etc. In this work, a thermal network model considering the thermal crosstalk of neighboring devices is proposed, which can accurately calculate the self-heating and thermal crosstalk. The electrical and thermal characteristics of NSFETs and CFETs are compared, and it is found that CFETs have more severe self-heating and thermal crosstalk. The electro-thermal characteristics of inverters, logic gates and ring oscillators composed of NSFETs and CFETs are further investigated. Compared with NSFETs, logic gates and ring oscillators composed of CFETs are more seriously affected by self-heating and should be given extra attention. The thermal network model proposed in this paper can be further used to study the thermal optimization strategy of devices and circuits to enhance the electrical performance, achieving the design technology co-optimizations (DTCO).