Topology-Aware Virtualization over Inter-Core Connected Neural Processing Units
Dahu Feng, Erhu Feng, Dong Du, Pinjie Xu, Yubin Xia, Haibo Chen, Rong Zhao

TL;DR
This paper presents vNPU, a novel virtualization framework for inter-core connected neural processing units that improves resource utilization and performance in AI accelerators by integrating topology-aware techniques.
Contribution
It introduces the first comprehensive virtualization design for inter-core connected NPUs, incorporating route, memory virtualization, and topology mapping techniques.
Findings
Up to 2x performance improvement over existing methods
Only 2% additional hardware cost
Effective resource utilization in AI accelerators
Abstract
With the rapid development of artificial intelligence (AI) applications, an emerging class of AI accelerators, termed Inter-core Connected Neural Processing Units (NPU), has been adopted in both cloud and edge computing environments, like Graphcore IPU, Tenstorrent, etc. Despite their innovative design, these NPUs often demand substantial hardware resources, leading to suboptimal resource utilization due to the imbalance of hardware requirements across various tasks. To address this issue, prior research has explored virtualization techniques for monolithic NPUs, but has neglected inter-core connected NPUs with the hardware topology. This paper introduces vNPU, the first comprehensive virtualization design for inter-core connected NPUs, integrating three novel techniques: (1) NPU route virtualization, which redirects instruction and data flow from virtual NPU cores to physical ones,…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Neural Networks and Applications · Neural Networks and Reservoir Computing
