Hardware-Aware Neural Architecture Search for Encrypted Traffic Classification on Resource-Constrained Devices

TL;DR

This paper introduces a hardware-aware neural architecture search method to develop a lightweight, accurate DNN for encrypted traffic classification on resource-limited IoT devices, achieving high accuracy with minimal resource usage.

Contribution

The paper presents a novel hardware-aware neural architecture search approach tailored for encrypted traffic classification on constrained devices, optimizing model size and efficiency while maintaining high accuracy.

Findings

Achieves 96.60% accuracy with 88.26K parameters and 10.08M FLOPs.

Reduces model size and computation by up to 444-fold and 312-fold respectively.

Deploys successfully on STM32 microcontrollers for low-latency inference.

Abstract

This paper presents a hardware-efficient deep neural network (DNN), optimized through hardware-aware neural architecture search (HW-NAS); the DNN supports the classification of session-level encrypted traffic on resource-constrained Internet of Things (IoT) and edge devices. Thanks to HW-NAS, a 1D convolutional neural network (CNN) is tailored on the ISCX VPN-nonVPN dataset to meet strict memory and computational limits while achieving robust performance. The optimized model attains 96.60% accuracy with just 88.26K parameters, 10.08M FLOPs, and a maximum tensor size of 20.12K. Compared to state-of-the-art models, it achieves reductions of up to 444-fold, 312-fold, and 15-fold in these metrics, respectively, minimizing memory footprint and runtime requirements. The model also achieves up to 99.86% across multiple VPN and traffic classification (TC) tasks; it further generalizes to external benchmarks with up to 99.98% accuracy on USTC-TFC and QUIC NetFlow. In addition, an in-depth study of header-level preprocessing confirms that the optimized model can provide performance across a wide range of configurations, even in scenarios with stricter privacy considerations. Likewise, a reduction in the length of sessions of up to 75% yields significant improvements in efficiency, while maintaining high accuracy with only a negligible drop of 1-2%. However, the importance of careful preprocessing and session length selection in the classification of raw traffic data is still present, as improper settings or aggressive reductions can cause a 7% reduction in accuracy. The quantized architecture was deployed on STM32 microcontrollers and evaluated across input sizes; results confirm that the efficiency gains from shorter sessions translate to practical, low-latency embedded inference. These findings demonstrate the method's practicality for encrypted traffic analysis in constrained IoT networks.