A Theory-driven Interpretation and Elaboration of Verification and Validation

TL;DR

This paper develops a formal, logic-based theory of verification and validation in systems engineering, clarifying their roles as knowledge-building activities through precise definitions and a structured framework.

Contribution

It introduces a novel formal framework using dynamic epistemic modal logic to rigorously define and analyze V&V processes in systems engineering.

Findings

Provides formal definitions of verification and validation.

Clarifies the conceptual relationship between evidence and knowledge.

Addresses ambiguities in traditional V&V practices.

Abstract

This paper presents a formal theory of verification and validation (V&V) within systems engineering, grounded in the axiom that V&V are fundamentally knowledge-building activities. Using dynamic epistemic modal logic, we develop precise definitions of verification and validation, articulating their roles in confirming and contextualizing knowledge about systems. The theory formalizes the interplay between epistemic states, evidence, and reasoning processes, allowing for the derivation of theorems that clarify the conceptual underpinnings of V&V. By providing a formal foundation, this work addresses ambiguities in traditional V&V practices, offering a structured framework to enhance precision and consistency in systems engineering methodologies. The insights gained have implications for both academic research and practical applications, fostering a deeper understanding of V&V as critical components of engineering knowledge generation.