HP2C-DT: High-Precision High-Performance Computer-enabled Digital Twin
E. Iraola, M. Garc\'ia-Lorenzo, F. Lordan-Gomis, F. Rossi, E. Prieto-Araujo, R. M. Badia

TL;DR
This paper introduces HP2C-DT, an architecture integrating high-performance computing into digital twins to enhance responsiveness and computational capacity, demonstrated through a power grid case study.
Contribution
It presents a novel HPC-enabled digital twin architecture and a working implementation that dynamically allocates tasks across edge, cloud, and HPC resources.
Findings
Reduces communication bandwidth by an order of magnitude
Doubles response times through dynamic offloading
Maintains near-ideal strong scaling for compute workflows
Abstract
Digital twins are transforming the way we monitor, analyze, and control physical systems, but designing architectures that balance real-time responsiveness with heavy computational demands remains a challenge. Cloud-based solutions often struggle with latency and resource constraints, while edge-based approaches lack the processing power for complex simulations and data-driven optimizations. To address this problem, we propose the High-Precision High-Performance Computer-enabled Digital Twin (HP2C-DT) reference architecture, which integrates High-Performance Computing (HPC) into the computing continuum. Unlike traditional setups that use HPC only for offline simulations, HP2C-DT makes it an active part of digital twin workflows, dynamically assigning tasks to edge, cloud, or HPC resources based on urgency and computational needs. Furthermore, to bridge the gap between theory and…
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