FPGA-Based Multiplier with a New Approximate Full Adder for Error-Resilient Applications
Ali Ranjbar, Elham Esmaeili, Roghayeh Rafieisangari, Nabiollah Shiri

TL;DR
This paper introduces a novel approximate multiplier using a new full adder design, significantly reducing power consumption and delay, suitable for error-resilient applications like image filtering on FPGA.
Contribution
It presents a new approximate full adder and multiplier design that improves speed and power efficiency for FPGA-based signal processing applications.
Findings
Achieves 56.09% power reduction and 73.02% PDP improvement.
Provides more accurate results with higher PSNR and SSIM.
Reduces power consumption by 33.33% in mean filter implementation.
Abstract
Electronic devices primarily aim to offer low power consumption, high speed, and a compact area. The performance of very large-scale integration (VLSI) devices is influenced by arithmetic operations, where multiplication is a crucial operation. Therefore, a high-speed multiplier is essential for developing any signal-processing module. Numerous multipliers have been reviewed in existing literature, and their speed is largely determined by how partial products (PPs) are accumulated. To enhance the speed of multiplication beyond current methods, an approximate adder-based multiplier is introduced. This approach allows for the simultaneous addition of PPs from two consecutive bits using a novel approximate adder. The proposed multiplier is utilized in a mean filter structure and implemented in ISE Design Suite 14.7 using VHDL and synthesized on the Xilinx Spartan3-XC3S400 FPGA board.…
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Taxonomy
TopicsLow-power high-performance VLSI design · Embedded Systems Design Techniques · VLSI and FPGA Design Techniques
