Engineering Cryogenic FETs: Addressing SCEs and Impact of Interface Traps Down to 2 K Temperature

TL;DR

This study models and benchmarks cryogenic bulk-FETs from 2 K to 300 K, revealing how interface traps and their distribution affect device performance and SCEs, guiding cryogenic CMOS design.

Contribution

It introduces an experimentally calibrated TCAD framework that incorporates interface-trap effects across a wide temperature range for cryogenic FETs.

Findings

Interface traps increase threshold voltage and suppress subthreshold conduction at cryogenic temperatures.

Trap distribution spatial standard deviation modulates SCEs and device barriers.

Predictions closely match experimental data at 4.2 K, 77 K, and 300 K.

Abstract

This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from $T = 2$ K to 300 K. For a 28-nm node device, carrier transport is predominantly ballistic at $T = 2$ K and becomes quasi-ballistic as temperature increases. At cryogenic temperatures, higher interface-trap densities increase the effective threshold voltage and suppress subthreshold conduction. However, when the ON-state bias is adjusted to account for the trap-induced $V_t$ shift, interface traps are found to \emph{worsen} $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$ along with degrading the subthreshold swing (SS) and reducing mobility across all temperatures. The spatial standard deviation $\sigma$ of the trap distribution modulates these behaviors: highly localized traps ($\sigma \sim 1$--$2$ nm) exacerbate short-channel effects (SCEs), whereas broader, nearly uniform distributions ($\sigma \ge 50$ nm) elevate the entire barrier and suppress SCEs until saturation as $\sigma \to L_g$. The TCAD predictions closely match experimental data at 4.2 K, 77 K, and 300 K, providing design guidelines to optimize $I_{\mathrm{ON}}/I_{\mathrm{OFF}}$, SS, mobility, and DIBL for cryogenic CMOS technology nodes.