Fault-Tolerant Stabilizer Measurements in Surface Codes with Three-Qubit Gates

TL;DR

This paper demonstrates that surface code stabilizer measurements can be made fault-tolerant using three-qubit gates, potentially reducing error rates and increasing thresholds in quantum error correction.

Contribution

It introduces a fault-tolerant stabilizer measurement protocol utilizing three-qubit gates, expanding the capabilities of surface codes beyond traditional two-qubit gate limitations.

Findings

Lower circuit depth with three-qubit gates reduces fault locations.

Logical error rate can be up to ten times lower with three-qubit gates.

Threshold error rate increases from approximately 0.76% to 1.05%.

Abstract

Quantum error correction (QEC) is considered a deciding component in enabling practical quantum computing. Stabilizer codes, and in particular topological surface codes, are promising candidates for implementing QEC by redundantly encoding quantum information. While it is widely believed that a strictly fault-tolerant protocol can only be implemented using single- and two-qubit gates, several quantum computing platforms, based on trapped ions, neutral atoms and also superconducting qubits support native multi-qubit operations, e.g. using multi-ion entangling gates, Rydberg blockade or parallelized tunable couplers, respectively. In this work, we show that stabilizer measurement circuits for unrotated surface codes can be fault-tolerant using single auxiliary qubits and three-qubit gates. These gates enable lower-depth circuits leading to fewer fault locations and potentially shorter QEC cycle times. Concretely, we find that in an optimistic parameter regime where fidelities of three-qubit gates are the same as those of two-qubit gates, the logical error rate can be up to one order of magnitude lower and the threshold can be significantly higher, increasing from $\approx 0.76 \%$ to $\approx 1.05 \%$. Our results, which are applicable to a wide range of platforms, thereby motivate further investigation into multi-qubit gates as components for fault-tolerant QEC, as they can lead to substantial advantages in terms of time and physical qubit resources required to reach a target logical error rate.