Frequency as a Clock: Synchronization and Intrinsic Recovery in Graphene Transistor Dynamics

TL;DR

This paper introduces a unified dynamic model for graphene transistors that explains hysteresis and memory effects by analyzing intrinsic relaxation and charge transfer, aiding the design of advanced graphene electronics.

Contribution

It presents a comprehensive model capturing both intrinsic and externally driven charge dynamics in GFETs, clarifying the physical origins of hysteresis and memory effects.

Findings

Identifies two regimes: intrinsic relaxation and frequency-locked response.

Explains loop invariance in floating-gate structures via displacement current.

Predicts hysteresis loop evolution under various driving conditions.

Abstract

Hysteresis and memory effects in graphene field-effect transistors (GFETs) offer unique opportunities for neuromorphic computing, sensing, and memory applications, yet their physical origins remain debated due to competing volatile and nonvolatile interpretations. Here, we present a unified dynamic model that captures the essential physics of the GFET response under periodic gate modulation, accounting for both intrinsic relaxation processes and externally driven charge transfer. By modeling non-equilibrium carrier dynamics as a competition between injection and reabsorption rates, we uncover two distinct regimes: one governed by intrinsic, frequency-independent relaxation and another exhibiting frequency-locked behavior where the response is tied to the external drive. This distinction resolves apparent nonvolatile effects and explains loop invariance in floating-gate structures via displacement current-driven charge injection. Our framework predicts the evolution of the hysteresis loop shape, amplitude, and direction across a wide range of driving conditions, offering a versatile tool for interpreting experimental results and guiding the design of next-generation graphene-based electronic systems.