Dual-Material Double-Gate Source-Pocket Tunnel Field Effect Transistor with Homogeneous Gate Dielectric: Computational Analysis of Structural and Material Parameters for Enhanced Performance

TL;DR

This study uses TCAD simulations to optimize a silicon-based dual-material double-gate TFET with a source-pocket structure and homogeneous dielectric, achieving high performance for low-power electronics.

Contribution

It introduces a simplified, silicon-based DMDG-SP TFET design with homogeneous gate dielectric, demonstrating enhanced performance through detailed simulation analysis.

Findings

6.7x higher ON current with pocket inclusion

45% increase in ON current with dual-material gates

Achieves ON/OFF ratio of 2.05×10^13 and subthreshold slope of 6.29 mV/decade

Abstract

Dual-material double-gate tunnel field effect transistor (DMDG TFET) is a promising candidate for low-power, high-speed electronics due to enhanced electrostatic control and superior switching characteristics. Integrating a pocket region between the source and channel-doped oppositely to the source-further improves tunneling efficiency by modulating the electric field at the tunneling junction. This combined architecture, termed the DMDG source-pocket TFET (DMDG-SP TFET), achieves higher ON current and reduced subthreshold swing compared to conventional TFETs. Previous DMDG-SP TFET designs primarily use heterogeneous gate dielectrics, composed of two stacked insulators to enhance gate control and tunneling modulation. However, such hetero gate dielectrics increase fabrication complexity and may degrade device reliability due to material incompatibility. This work proposes a silicon-based DMDG-SP TFET employing a homogenous gate dielectric, investigated through Silvaco Atlas-based 2-D TCAD simulations, aiming to simplify fabrication without compromising performance. Presence of the pocket results in 6.7x higher ON current and 1.7x lower subthreshold swing compared to pocket-less devices. Dual-material gates boost ON current by 45% and improve the ON/OFF current ratio by 59% compared to single-material gates in pocket-based devices. Detailed simulations analyze effects of gate metal work functions and lengths, gate dielectric constant, and doping densities and lengths of all regions. The optimized device achieves an ON current of 3.16*10^-4 A/um, OFF current of 1.54*10^-17 A/um, ON/OFF ratio of 2.05*10^13, and subthreshold slope of 6.29 mV/decade. These findings offer critical insights for designing manufacturable, high-performance homojunction silicon-based DMDG-SP TFETs with homogeneous gate dielectrics for next-generation low-power integrated circuits.