A Survey on LUT-based Deep Neural Networks Implemented in FPGAs

TL;DR

This survey reviews LUT-based FPGA implementations of deep neural networks, highlighting their advantages in resource utilization and latency reduction for edge applications, and discusses future research directions.

Contribution

It provides a comprehensive overview of LUT-based DNN architectures on FPGAs, including their evolution, design methodologies, and performance trade-offs.

Findings

LUT-based DNNs improve resource utilization on FPGAs.

LUT-based DNNs reduce inference latency.

The survey outlines future research directions.

Abstract

Low-latency, energy-efficient deep neural networks (DNNs) inference are critical for edge applications, where traditional cloud-based deployment suffers from high latency and security risks. Field-Programmable Gate Arrays (FPGAs) offer a compelling solution, balancing reconfigurability, power efficiency, and real-time performance. However, conventional FPGA-based DNNs rely heavily on digital signal processing (DSP) blocks for multiply-accumulate (MAC) operations, limiting scalability. LUT-based DNNs address this challenge by fully leveraging FPGA lookup tables (LUTs) for computation, improving resource utilization and reducing inference latency. This survey provides a comprehensive review of LUT-based DNN architectures, including their evolution, design methodologies, and performance trade-offs, while outlining promising directions for future research.