VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

TL;DR

VeriLoC introduces a novel approach that uses large language model embeddings to predict line-level hardware design quality metrics directly from Verilog code, enabling early detection of potential issues.

Contribution

It is the first method to predict hardware design quality at the line-level directly from Verilog using LLM-based embeddings and classifiers.

Findings

Achieves F1-scores of 0.86-0.95 for congestion and timing prediction.

Reduces mean absolute percentage error from 14-18% to 4%.

Demonstrates effectiveness of LLM embeddings for hardware quality prediction.

Abstract

Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a commonly used programming language for hardware design). It is especially important yet complex to predict individual lines of code that cause timing violations or downstream routing congestion. Prior works have tried approaches like converting Verilog into an intermediate graph representation and using LLM embeddings alongside other features to predict module-level quality, but did not consider line-level quality prediction. We propose VeriLoC, the first method that predicts design quality directly from Verilog at both the line- and module-level. To this end, VeriLoC leverages recent Verilog code-generation LLMs to extract local line-level and module-level embeddings, and train downstream classifiers/regressors on concatenations of these embeddings. VeriLoC achieves high F1-scores of 0.86-0.95 for line-level congestion and timing prediction, and reduces the mean average percentage error from 14% - 18% for SOTA methods down to only 4%. We believe that VeriLoC embeddings and insights from our work will also be of value for other predictive and optimization tasks for complex hardware design.