Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing

TL;DR

This paper analyzes RISC-V's modular design and demonstrates its advantages in embedded systems, highlighting the potential for custom accelerators and showing a 17% power efficiency improvement over ARM Cortex-M0.

Contribution

It provides a detailed analysis of RISC-V's architecture, implementation challenges, and performance, including a custom DSP accelerator design for edge computing.

Findings

RISC-V offers a 17% power reduction compared to ARM Cortex-M0.

Cycle-accurate simulation evaluates performance metrics.

Open-standard RISC-V enables flexible domain-specific optimizations.

Abstract

This paper presents a comprehensive analysis of the RISC-V instruction set architecture, focusing on its modular design, implementation challenges, and performance characteristics. We examine the RV32I base instruction set with extensions for multiplication (M) and atomic operations (A). Through cycle-accurate simulation of a pipelined implementation, we evaluate performance metrics including CPI (cycles per instruction) and power efficiency. Our results demonstrate RISC-V's advantages in embedded systems and its scalability for custom accelerators. Comparative analysis shows a 17% reduction in power consumption compared to ARM Cortex-M0 implementations in similar process nodes. The open-standard nature of RISC-V provides significant flexibility for domain-specific optimizations.