High Throughput Event Filtering: The Interpolation-based DIF Algorithm Hardware Architecture
Marcin Kowalczyk, Tomasz Kryjak

TL;DR
This paper presents a high-throughput FPGA hardware architecture for the DIF event filtering algorithm, significantly improving processing speed while maintaining high filtering accuracy, and introduces a new dataset for evaluation.
Contribution
The paper introduces a novel FPGA-based hardware architecture for the DIF filter, achieving unprecedented throughput and providing a new high-resolution event dataset for benchmarking.
Findings
Achieved 403.39 to 428.45 million events per second throughput.
Maintained high filtering accuracy with AUROC between 0.844 and 0.999.
Outperformed existing solutions in speed with comparable accuracy.
Abstract
In recent years, there has been rapid development in the field of event vision. It manifests itself both on the technical side, as better and better event sensors are available, and on the algorithmic side, as more and more applications of this technology are proposed and scientific papers are published. However, the data stream from these sensors typically contains a significant amount of noise, which varies depending on factors such as the degree of illumination in the observed scene or the temperature of the sensor. We propose a hardware architecture of the Distance-based Interpolation with Frequency Weights (DIF) filter and implement it on an FPGA chip. To evaluate the algorithm and compare it with other solutions, we have prepared a new high-resolution event dataset, which we are also releasing to the community. Our architecture achieved a throughput of 403.39 million events per…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Radiation Effects in Electronics · Advanced Data Storage Technologies
