VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration

TL;DR

VCDiag is a machine learning-based framework that efficiently classifies failing waveforms and identifies probable failure points in RTL simulations, significantly reducing data size and aiding failure triage.

Contribution

It introduces a novel signal selection and compression method for waveform classification, enabling accurate failure analysis in large, complex designs.

Findings

Achieves over 94% accuracy in identifying likely failure modules.

Reduces raw waveform data size by over 120 times while maintaining classification features.

Demonstrates adaptability across various Verilog/SystemVerilog designs.

Abstract

Failure triage in design functional verification is critical but time-intensive, relying on manual specification reviews, log inspections, and waveform analyses. While machine learning (ML) has improved areas like stimulus generation and coverage closure, its application to RTL-level simulation failure triage, particularly for large designs, remains limited. VCDiag offers an efficient, adaptable approach using VCD data to classify failing waveforms and pinpoint likely failure locations. In the largest experiment, VCDiag achieves over 94% accuracy in identifying the top three most likely modules. The framework introduces a novel signal selection and statistical compression approach, achieving over 120x reduction in raw data size while preserving features essential for classification. It can also be integrated into diverse Verilog/SystemVerilog designs and testbenches.