AEQUAM: Accelerating Quantum Algorithm Validation through FPGA-Based Emulation

TL;DR

AEQUAM is a novel FPGA-based emulation toolchain that accelerates quantum circuit validation by translating OpenQASM into hardware descriptions, enabling scalable and efficient quantum circuit simulation.

Contribution

It introduces a comprehensive FPGA-based emulation architecture with a compiler, software models, and RTL generator, improving scalability and accessibility for quantum circuit verification.

Findings

Achieves better scalability than existing emulators.

Validated using the mqt bench quantum circuit benchmark.

Supports customization of emulated qubits and parallelization levels.

Abstract

This work presents AEQUAM (Area Efficient QUAntum eMulation), a toolchain that enables faster and more accessible quantum circuit verification. It consists of a compiler that translates OpenQASM 2.0 into RISC-like instructions, Cython software models for selecting number representations and simulating circuits, and a VHDL generator that produces RTL descriptions for FPGA-based hardware emulators. The architecture leverages a SIMD approach to parallelize computation and reduces complexity by exploiting the sparsity of quantum gate matrices. The VHDL generator allows customization of the number of emulated qubits and parallelization levels to meet user requirements. Synthesized on an Altera Cyclone 10LP FPGA with a 20-bit fixed-point representation and nearest-type approximation, the architecture demonstrates better scalability than other state-of-the-art emulators. Specifically, the emulator has been validated by exploiting the well consolidated benchmark of mqt bench framework.