ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction

TL;DR

ARIANNA is an automated design flow that optimizes fabric customization for embedded FPGA-based logic redaction, significantly reducing overheads and increasing fabric utilization for IP protection in ICs.

Contribution

It introduces a comprehensive, automated flow with heuristics for fabric customization, improving security and efficiency in logic redaction compared to prior generic solutions.

Findings

Up to 3.3x lower overheads with ARIANNA

Up to 4x higher fabric utilization

Effective heuristics outperform exhaustive methods

Abstract

In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft countermeasures is hard to achieve. Using embedded configurable logic allows designers to completely hide the functionality of selected design portions from parties that do not have access to the configuration string (bitstream). However, the design space of redacted solutions is huge, with trade-offs between the portions selected for redaction and the configuration of the configurable embedded logic. We propose ARIANNA, a complete flow that aids the designer in all the stages, from selecting the logic to be hidden to tailoring the bespoke fabrics for the configurable logic used to hide it. We present a security evaluation of the considered fabrics and introduce two heuristics for the novel bespoke fabric flow. We evaluate the heuristics against an exhaustive approach. We also evaluate the complete flow using a selection of benchmarks. Results show that using ARIANNA to customize the redaction fabrics yields up to 3.3x lower overheads and 4x higher eFPGA fabric utilization than a one-fits-all fabric as proposed in prior works.