Design and Validation of the Digital Receiver System for the next-generation radio interferometer

TL;DR

This paper details the design and validation of a high-speed digital receiver system for next-generation radio interferometers, demonstrating real-time processing, interference analysis, and precise delay compensation through experiments.

Contribution

It introduces a novel FPGA-based digital receiver supporting 8 inputs at 4GHz sampling, with innovative delay compensation methods validated through field experiments.

Findings

Sub-nanosecond delay consistency between methods

Successful observation of celestial and satellite signals

Demonstrated suitability for future radio telescope projects

Abstract

This paper presents the design and validation of a digital receiver system developed for the next-generation radio interferometer projects. The receiver supports 8 analog inputs with 12-bit, 4GHz sampling and performs real-time signal processing using FPGA-based channelization. Field experiments were conducted to observe the Sun, a satellite beacon, and Cassiopeia A. Interference fringes were analyzed and modeled. Time delay compensation was implemented in two ways: theoretical calculation and Gaussian Process Regression (GPR) fitting. Results show sub-nanosecond consistency between the two methods. The field experiments demonstrate the receiver's suitability for future radio telescopes such as the BINGO-ABDUS project.