QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation

TL;DR

This paper introduces CodeV-R1, a reinforcement learning framework for training large language models to generate Verilog hardware descriptions from natural language, overcoming verification and data scarcity challenges, and achieving state-of-the-art performance.

Contribution

The paper presents a novel RLVR framework with a rule-based testbench, a data synthesis method, and a two-stage training pipeline, significantly improving Verilog generation accuracy.

Findings

Achieves 68.6% pass@1 on VerilogEval v2

Surpasses prior state-of-the-art by 12-20%

Outperforms larger models like DeepSeek-R1 on RTLLM

Abstract

Large language models (LLMs) trained via reinforcement learning with verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit, automatable verification, such as software programming and mathematical problems. Extending RLVR to electronic design automation (EDA), especially automatically generating hardware description languages (HDLs) like Verilog from natural-language (NL) specifications, however, poses three key challenges: the lack of automated and accurate verification environments, the scarcity of high-quality NL-code pairs, and the prohibitive computation cost of RLVR. To this end, we introduce CodeV-R1, an RLVR framework for training Verilog generation LLMs. First, we develop a rule-based testbench generator that performs robust equivalence checking against golden references. Second, we propose a round-trip data synthesis method that pairs open-source Verilog snippets with LLM-generated NL descriptions, verifies code-NL-code consistency via the generated testbench, and filters out inequivalent examples to yield a high-quality dataset. Third, we employ a two-stage "distill-then-RL" training pipeline: distillation for the cold start of reasoning abilities, followed by adaptive DAPO, our novel RLVR algorithm that can reduce training cost by adaptively adjusting sampling rate. The resulting model, CodeV-R1-7B, achieves 68.6% and 72.9% pass@1 on VerilogEval v2 and RTLLM v1.1, respectively, surpassing prior state-of-the-art by 12~20%, while even exceeding the performance of 671B DeepSeek-R1 on RTLLM. We have released our model, training code, and dataset to facilitate research in EDA and LLM communities.