Low Crosstalk in a Scalable Superconducting Quantum Lattice

TL;DR

This paper presents a scalable 4x4 superconducting qubit lattice with low crosstalk, achieved through innovative design and 3D integration, advancing the development of large-scale quantum processors.

Contribution

The work introduces a tileable 3D-integrated circuit architecture with off-chip inductive shunting to reduce crosstalk in a 4x4 qubit lattice, demonstrating low error rates and high uniformity.

Findings

Achieved low crosstalk in a 16-qubit lattice

Demonstrated uniform qubit parameters with low frequency spread

Maintained low single-qubit gate errors across the device

Abstract

Superconducting quantum circuits are a key platform for advancing quantum information processing and simulation. Scaling efforts currently encounter challenges such as Josephson-junction fabrication yield, design frequency targeting, and crosstalk arising both from spurious microwave modes and intrinsic interactions between qubits. We demonstrate a scalable 4x4 square lattice with low crosstalk, comprising 16 fixed-frequency transmon qubits with nearest-neighbor capacitive coupling that is implemented in a tileable, 3D-integrated circuit architecture with off-chip inductive shunting to mitigate spurious enclosure modes. We report on the design and comprehensive characterization, and show that our implementation achieves targeted device parameters with very low frequency spreads and simultaneous single-qubit gate errors across the device. Our results provide a promising pathway toward a scalable, low-crosstalk superconducting lattice topology with high qubit connectivity for quantum error correction and simulation.