iDSE: Navigating Design Space Exploration in High-Level Synthesis Using LLMs
Runkai Li, Jia Xiong, Xi Wang

TL;DR
This paper introduces iDSE, an LLM-aided framework for high-level synthesis design space exploration that significantly improves efficiency and quality of Pareto front approximation by leveraging LLMs' reasoning capabilities.
Contribution
iDSE is the first framework to utilize large language models for navigating HLS design space, achieving faster convergence and better results than traditional heuristic methods.
Findings
Outperforms heuristic DSE methods by 5.1x to 16.6x in proximity to Pareto front.
Matches NSGA-II performance with only 4.6% of the explored designs.
Demonstrates the potential of LLMs in hardware optimization and multiobjective search.
Abstract
High-Level Synthesis (HLS) serves as an agile hardware development tool that streamlines the circuit design by abstracting the register transfer level into behavioral descriptions, while allowing designers to customize the generated microarchitectures through optimization directives. However, the combinatorial explosion of possible directive configurations yields an intractable design space. Traditional design space exploration (DSE) methods, despite adopting heuristics or constructing predictive models to accelerate Pareto-optimal design acquisition, still suffer from prohibitive exploration costs and suboptimal results. Addressing these concerns, we introduce iDSE, the first LLM-aided DSE framework that leverages HLS design quality perception to effectively navigate the design space. iDSE intelligently pruns the design space to guide LLMs in calibrating representative initial sampling…
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Taxonomy
TopicsEmbedded Systems Design Techniques · VLSI and FPGA Design Techniques · Low-power high-performance VLSI design
