VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification

TL;DR

VeriThoughts introduces a dataset and benchmark framework for reasoning-based Verilog code generation, emphasizing formal verification to ensure correctness and facilitate automated hardware design from high-level specifications.

Contribution

The paper presents a new dataset, a benchmark framework based on formal verification, and specialized models for Verilog generation, advancing automated and correct hardware design.

Findings

New dataset for reasoning-based Verilog generation

Benchmark framework utilizing formal verification methods

Models optimized for Verilog code synthesis

Abstract

This paper introduces VeriThoughts, a novel dataset designed for reasoning-based Verilog code generation. We establish a new benchmark framework grounded in formal verification methods to evaluate the quality and correctness of generated hardware descriptions. Additionally, we present a suite of specialized small-scale models optimized specifically for Verilog generation. Our work addresses the growing need for automated hardware design tools that can produce verifiably correct implementations from high-level specifications, potentially accelerating the hardware development process while maintaining rigorous correctness guarantees. Our code and data are available at \href{https://github.com/wilyub/VeriThoughts}{this URL}.