ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection

TL;DR

ReChisel leverages large language models with a reflection mechanism to improve automatic Chisel code generation, making HDL development more efficient and scalable.

Contribution

This work introduces ReChisel, an LLM-based system with reflection and escape mechanisms, specifically designed for effective Chisel HDL code generation.

Findings

ReChisel significantly increases code generation success rates.

Performance is comparable to state-of-the-art Verilog code generators.

Reflection improves iterative refinement of generated code.

Abstract

Coding with hardware description languages (HDLs) such as Verilog is a time-intensive and laborious task. With the rapid advancement of large language models (LLMs), there is increasing interest in applying LLMs to assist with HDL coding. Recent efforts have demonstrated the potential of LLMs in translating natural language to traditional HDL Verilog. Chisel, a next-generation HDL based on Scala, introduces higher-level abstractions, facilitating more concise, maintainable, and scalable hardware designs. However, the potential of using LLMs for Chisel code generation remains largely unexplored. This work proposes ReChisel, an LLM-based agentic system designed to enhance the effectiveness of Chisel code generation. ReChisel incorporates a reflection mechanism to iteratively refine the quality of generated code using feedback from compilation and simulation processes, and introduces an escape mechanism to break free from non-progress loops. Experiments demonstrate that ReChisel significantly improves the success rate of Chisel code generation, achieving performance comparable to state-of-the-art LLM-based agentic systems for Verilog code generation.