An Ultra-Low Power and Fast Ising Machine using Voltage-Controlled Magnetoresistive Random Access Memory
Sai Li, Yihao Zhang, Albert Lee, Zheng Zhu, Lang Zeng, Peng Wang, Lei Gao, Di Wu, Weisheng Zhao

TL;DR
This paper introduces a novel chip-level Ising machine using voltage-controlled magnetoresistive RAM, achieving ultra-low power consumption and high speed, suitable for solving complex optimization problems efficiently.
Contribution
The work presents the first voltage-controlled spintronic Ising machine with sub-1 ns latency and 40 fJ energy per update, outperforming previous implementations significantly.
Findings
Latency below 1 nanosecond
Energy consumption under 40 femtojoules per spin update
Solves real-world optimization problems with high efficiency
Abstract
Physics-inspired computing paradigms, such as Ising machines, are emerging as promising hardware alternatives to traditional von Neumann architectures for tackling computationally intensive combinatorial optimization problems (COPs). While quantum, optical, and electronic devices have garnered significant attention for their potential in realizing Ising machines, their translation into practical systems for industry-relevant applications remains challenging, with each approach facing specific limitations in power consumption and speed. To address this challenge, we report the first chip-level spintronic Ising machine using voltage-controlled magnetoresistive random access memory. The core of our design leverages magnetic tunnel junctions (MTJs) driven by the voltage-controlled magnetic anisotropy effect to realize the probabilistic update of Ising spins through a new mechanism. It…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Advanced Memory and Neural Computing · Parallel Computing and Optimization Techniques
