Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing

TL;DR

This paper presents a lightweight, precision-scalable posit/IEEE-754 arithmetic implementation in RISC-V cores, enabling efficient transprecision computing with significant hardware savings and performance gains.

Contribution

It introduces a unified hardware solution for posit and IEEE-754 arithmetic in RISC-V, supporting multi/mixed-precision and dynamic exponent sizes for transprecision computing.

Findings

47.9% reduction in LUTs compared to state-of-the-art

57.4% reduction in FFs compared to state-of-the-art

Up to 2.54× throughput improvement in GEMM kernels

Abstract

While posit format offers superior dynamic range and accuracy for transprecision computing, its adoption in RISC-V processors is hindered by the lack of a unified solution for lightweight, precision-scalable, and IEEE-754 arithmetic compatible hardware implementation. To address these challenges, we enhance RISC-V processors by 1) integrating dedicated posit codecs into the original FPU for lightweight implementation, 2) incorporating multi/mixed-precision support with dynamic exponent size for precision-scalability, and 3) reusing and customizing ISA extensions for IEEE-754 compatible posit operations. Our comprehensive evaluation spans the modified FPU, RISC-V core, and SoC levels. It demonstrates that our implementation achieves 47.9% LUTs and 57.4% FFs reduction compared to state-of-the-art posit-enabled RISC-V processors, while achieving up to 2.54$\times$ throughput improvement in various GEMM kernels.