High Throughput QC-LDPC Decoder With Optimized Schedule Policy in Layered Decoding

TL;DR

This paper proposes an optimized layered decoding schedule for QC-LDPC codes that balances high throughput, minimal hardware delay, and strong decoding performance, especially suited for 5G NR applications.

Contribution

It introduces a scheduling policy formulated as a TSP to optimize decoding delay and performance, with a refined graph approach for better results.

Findings

Reduced hardware delay in decoding process

Maintained high decoding performance for 5G NR LDPC codes

Effective scheduling sequence identified through TSP optimization

Abstract

In this study, a scheduling policy of layered decoding for quasi-cycle (QC) low-density parity-check (LDPC) codes with high throughput and good performance is designed. The influence of scheduling on the delay of the decoder's hardware implementation and on the decoding performance are considered simultaneously. Specifically, we analyze the idle time required under various scheduling sequences within a pipelined decoding architecture and formulate the problem as a traveling salesman problem (TSP) aiming at minimizing idle time. Furthermore, considering that different scheduling sequences can affect decoding performance, we refine the graph used to solve the TSP based on scheduling characteristics that promote improved decoding outcomes. Simulation results demonstrate that the identified scheduling sequence achieves a low number of hardware delays while maintaining excellent decoding performance for 5G New Radio (NR) LDPC codes.