Garibaldi: A Pairwise Instruction-Data Management for Enhancing Shared Last-Level Cache Performance in Server Workloads
Jaewon Kwon, Yongju Lee, Jiwan Kim, Enhyeok Jang, Hongju Kal, Won Woo Ro (Yonsei University, Seoul, Republic of Korea)

TL;DR
Garibaldi introduces a pairwise instruction-data cache management scheme that improves server workload performance by better preserving hot instructions and prefetching data, reducing LLC misses and frontend bottlenecks.
Contribution
This work presents a novel pairwise instruction-data management scheme, Garibaldi, that enhances LLC performance by coupling instruction and data access hotness and applying selective protection and prefetching.
Findings
Achieves 13.2% CPU performance improvement on baseline LLC
Achieves 6.1% CPU performance improvement on Mockingjay LLC
Effectively reduces instruction cache misses in server workloads
Abstract
Modern CPUs suffer from the frontend bottleneck because the instruction footprint of server workloads exceeds the private cache capacity. Prior works have examined the CPU components or private cache to improve the instruction hit rate. The large footprint leads to significant cache misses not only in the core and faster-level cache but also in the last-level cache (LLC). We observe that even with an advanced branch predictor and instruction prefetching techniques, a considerable amount of instruction accesses descend to the LLC. However, state-of-the-art LLC designs with elaborate data management overlook handling the instruction misses that precede corresponding data accesses. Specifically, when an instruction requiring numerous data accesses is missed, the frontend of a CPU should wait for the instruction fetch, regardless of how much data are present in the LLC. To preserve hot…
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