Current-Steering DAC Architecture Design for Amplitude Mismatch Error Minimization

TL;DR

This paper introduces a new digital-to-analog converter architecture that reduces amplitude mismatch errors by statistically minimizing distortion, using a novel weighting scheme and a heuristic codeword mapping algorithm.

Contribution

It presents a unique DAC weighting architecture and a heuristic mapping algorithm that improve static performance over traditional segmented DACs.

Findings

Simulations show reduced distortion compared to segmented DACs.

The architecture does not rely on power-of-two weightings.

Static performance improvements are demonstrated through Matlab simulations.

Abstract

We propose a novel digital-to-analog converter (DAC) weighting architecture that statistically minimizes the distortion caused by random current mismatches. Unlike binary, thermometer-coded, and segmented DACs, the current weights of the proposed architecture are not an integer power of 2 or any other integer number. We present a heuristic algorithm for a static mapping of DAC input codewords into corresponding DAC switches. High-level Matlab simulations are performed to illustrate the static performance improvement over the segmented structure.