TL;DR
This paper introduces a simulated annealing-based method to optimize QAOA circuit transpilation, significantly reducing gate count and depth on non-fully connected quantum hardware, thereby improving performance on noisy quantum devices.
Contribution
It presents a novel simulated annealing approach that enhances PTC and SWAP network encodings for QAOA circuits, outperforming existing transpilers at high connectivity thresholds.
Findings
Achieves up to 85% reduction in circuit depth for 120-qubit instances.
Reduces two-qubit gates by 28% on average.
Demonstrates improved performance on ibm_fez device up to 20 qubits.
Abstract
Mapping quantum approximate optimization algorithm (QAOA) circuits with non-trivial connectivity in fixed-layout quantum platforms such as superconducting-based quantum processing units (QPUs) requires a process of transpilation to match the quantum circuit on the given layout. This step is critical for reducing error rates when running on noisy QPUs. Two methodologies that improve the resource required to do such transpilation are the SWAP network and parity twine chains (PTC). These approaches reduce the two-qubit gate count and depth needed to represent fully connected circuits. In this work, a simulated annealing-based method is introduced that reduces the PTC and SWAP network encoding requirements in QAOA circuits with non-fully connected two-qubit gates. This method is benchmarked against various transpilers and demonstrates that, beyond specific connectivity thresholds, it…
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