Evaluating the impact of the L3 cache size of AMD EPYC CPUs on the performance of CFD applications
Marcin Lawenda, {\L}ukasz Szustak, L\'aszl\'o K\"ornyei, Flavio Cesar Cunha Galeazzo, Pawe{\l} Bratek

TL;DR
This study evaluates how different AMD EPYC CPU architectures, with varying L3 cache sizes, affect CFD application performance, highlighting the importance of cache capacity and memory bandwidth.
Contribution
It provides a comprehensive analysis of multiple AMD EPYC architectures' impact on CFD performance, emphasizing cache size and memory bandwidth effects.
Findings
Maximum performance linked to specific grid sizes and processor attributes.
L3 cache size significantly influences CFD application efficiency.
Profiling revealed hardware interactions affecting application performance.
Abstract
In this work, the authors focus on assessing the impact of the AMD EPYC processor architecture on the performance of CFD applications. Several generations of architectures were analyzed, such as Rome, Milan, Milan X, Genoa, Genoa X and Bergamo, characterized by a different number of cores (64-128), L3 cache size (256 - 1152 MB) and RAM type (8-channel DDR4 or 12-channel DDR5). The research was conducted based on the OpenFOAM application using two memory-bound models: motorBike and Urban Air Pollution. In order to compare the performance of applications on different architectures, the FVOPS (Finite VOlumes solved Per Second) metric was introduced, which allows a direct comparison of the performance on the different architectures. It was noticed that local maximum performance occurs in the grid sizes assigned to the processing process, which is related to individual processor attributes.…
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