Leveraging biased noise for more efficient quantum error correction at the circuit-level with two-level qubits

TL;DR

This paper demonstrates that leveraging residual bias in circuit-level noise, using bias-preserving CZ gates and a hybrid noise model, significantly improves quantum error correction efficiency and thresholds for two-level qubits.

Contribution

It introduces a hybrid biased-depolarizing noise model and shows how bias-preserving CZ gates enhance quantum error correction performance.

Findings

Bias-preserving CZ gates maintain residual bias up to η~5.

Using bias-aware gates increases code threshold by 90%.

Qubit footprint can be reduced by up to 75%.

Abstract

Tailoring quantum error correction codes (QECC) to biased noise has demonstrated significant benefits. However, most of the prior research on this topic has focused on code capacity noise models. Furthermore, a no-go theorem prevents the construction of CNOT gates for two-level qubits in a bias preserving manner which may, in principle, imply that noise bias cannot be leveraged in such systems. In this work, we show that a residual bias up to $\eta\sim$5 can be maintained in CNOT gates under certain conditions. Moreover, we employ controlled-phase (CZ) gates in syndrome extraction circuits and show how to natively implement these in a bias-preserving manner for a broad class of qubit platforms. This motivates the introduction of what we call a hybrid biased-depolarizing (HBD) circuit-level noise model which captures these features. We numerically study the performance of the XZZX surface code and observe that bias-preserving CZ gates are critical for leveraging biased noise. Accounting for the residual bias present in the CNOT gates, we observe an increase in the code threshold up to a $1.27\%$ physical error rate, representing a $90\%$ improvement. Additionally, we find that the required qubit footprint can be reduced by up to a $75\%$ at relevant physical error rates.