Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint

TL;DR

This paper introduces a simulation-guided approximate logic synthesis method that efficiently handles maximum error constraints, significantly improving speed and circuit quality for large-scale designs.

Contribution

It proposes a novel simulation-guided ALS flow that accelerates the process and scales to large benchmarks while ensuring maximum error constraints are met.

Findings

30.6x faster synthesis compared to state-of-the-art

18.2% reduction in circuit area

4.9% decrease in delay

Abstract

Approximate computing is an effective computing paradigm for improving the energy efficiency of error-tolerant applications. Approximate logic synthesis (ALS) is an automatic process to generate approximate circuits with reduced area, delay, and power, while satisfying user-specified error constraints. This paper focuses on ALS under the maximum error constraint. As an essential error metric that provides a worst-case error guarantee, the maximum error is crucial for many applications such as image processing and machine learning. This work proposes an efficient simulation-guided ALS flow that handles this constraint. It utilizes logic simulation to 1) prune local approximate changes (LACs) with large errors that violate the error constraint, and 2) accelerate the SAT-based LAC selection process. Furthermore, to enhance scalability, our ALS flow iteratively selects a set of promising LACs satisfying the error constraint to improve efficiency. The experimental results show that compared with the state-of-the-art method, our ALS flow accelerates by 30.6x, and further reduces the circuit area and delay by 18.2% and 4.9%, respectively. Notably, our flow scales to large EPFL benchmarks with up to 38540 nodes, which remain challenging for existing ALS methods tackling maximum error constraint.