Mitigating cosmic ray-like correlated events with a modular quantum processor

TL;DR

This study investigates how modular quantum processor architectures can reduce correlated errors caused by cosmic ray impacts, showing that physical separation between modules significantly decreases correlated decay events.

Contribution

The paper demonstrates that modular quantum computing architectures can effectively mitigate cosmic ray-like correlated errors, providing a new approach to enhance quantum processor reliability.

Findings

Strong correlation (>85%) within single modules

Low correlation (~2%) between separate modules

Modular design reduces chip-scale correlated errors

Abstract

Quantum processors based on superconducting qubits are being scaled to larger qubit numbers, enabling the implementation of small-scale quantum error correction codes. However, catastrophic chip-scale correlated errors have been observed in these processors, attributed to e.g. cosmic ray impacts, which challenge conventional error-correction codes such as the surface code. These events are characterized by a temporary but pronounced suppression of the qubit energy relaxation times. Here, we explore the potential for modular quantum computing architectures to mitigate such correlated energy decay events. We measure cosmic ray-like events in a quantum processor comprising a motherboard and two flip-chip bonded daughterboard modules, each module containing two superconducting qubits. We monitor the appearance of correlated qubit decay events within a single module and across the physically separated modules. We find that while decay events within one module are strongly correlated (over $85\%$), events in separate modules only display $\sim 2\%$ correlations. We also report coincident decay events in the motherboard and in either of the two daughterboard modules, providing further insight into the nature of these decay events. These results suggest that modular architectures, combined with bespoke error correction codes, offer a promising approach for protecting future quantum processors from chip-scale correlated errors.