An Overview of Arithmetic Adaptations for Inference of Convolutional Neural Networks on Re-configurable Hardware

TL;DR

This paper reviews various arithmetic adaptation strategies for deploying CNNs, specifically TinyYOLOv3, on FPGA hardware, focusing on optimization techniques like fusion, pruning, and quantization to improve efficiency.

Contribution

It presents best practice approaches for implementing TinyYOLOv3 on XILINX Artix-7 FPGA, combining multiple optimization techniques for enhanced performance.

Findings

Fusion of batch normalization improves computational efficiency.

Filter pruning reduces model complexity and resource usage.

Post-training quantization enables deployment on resource-constrained hardware.

Abstract

Convolutional Neural Networks (CNNs) have gained high popularity as a tool for computer vision tasks and for that reason are used in various applications. There are many different concepts, like single shot detectors, that have been published for detecting objects in images or video streams. However, CNNs suffer from disadvantages regarding the deployment on embedded platforms such as re-configurable hardware like Field Programmable Gate Arrays (FPGAs). Due to the high computational intensity, memory requirements and arithmetic conditions, a variety of strategies for running CNNs on FPGAs have been developed. The following methods showcase our best practice approaches for a TinyYOLOv3 detector network on a XILINX Artix-7 FPGA using techniques like fusion of batch normalization, filter pruning and post training network quantization.