Hardware-Adaptive and Superlinear-Capacity Memristor-based Associative Memory

TL;DR

This paper presents a hardware-adaptive memristor-based associative memory with significantly improved capacity, defect tolerance, and energy efficiency, capable of handling both binary and continuous patterns with superlinear scaling.

Contribution

It introduces a novel hardware-adaptive learning algorithm for memristor-based associative memory that enhances defect tolerance and capacity, extending to scalable multilayer architectures.

Findings

Achieves 3x capacity under 50% device faults

Enables superlinear capacity scaling ( N^{1.49} for binary patterns)

Reduces energy consumption by 8.8x and latency by 99.7%

Abstract

Brain-inspired computing aims to mimic cognitive functions like associative memory, the ability to recall complete patterns from partial cues. Memristor technology offers promising hardware for such neuromorphic systems due to its potential for efficient in-memory analog computing. Hopfield Neural Networks (HNNs) are a classic model for associative memory, but implementations on conventional hardware suffer from efficiency bottlenecks, while prior memristor-based HNNs faced challenges with vulnerability to hardware defects due to offline training, limited storage capacity, and difficulty processing analog patterns. Here we introduce and experimentally demonstrate on integrated memristor hardware a new hardware-adaptive learning algorithm for associative memories that significantly improves defect tolerance and capacity, and naturally extends to scalable multilayer architectures capable of handling both binary and continuous patterns. Our approach achieves 3x effective capacity under 50% device faults compared to state-of-the-art methods. Furthermore, its extension to multilayer architectures enables superlinear capacity scaling (\(\propto N^{1.49}\ for binary patterns) and effective recalling of continuous patterns (\propto N^{1.74}\ scaling), as compared to linear capacity scaling for previous HNNs. It also provides flexibility to adjust capacity by tuning hidden neurons for the same-sized patterns. By leveraging the massive parallelism of the hardware enabled by synchronous updates, it reduces energy by 8.8x and latency by 99.7% for 64-dimensional patterns over asynchronous schemes, with greater improvements at scale. This promises the development of more reliable memristor-based associative memory systems and enables new applications research due to the significantly improved capacity, efficiency, and flexibility.