2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology

TL;DR

This paper proposes a 2T1R memristor array architecture with regulated voltage and current sources for improved conductance control, addressing sneak path issues and enhancing neuromorphic computing efficiency.

Contribution

It introduces a novel 2T1R array architecture with regulated sources to improve conductance control and mitigate sneak path effects in memristor-based neuromorphic systems.

Findings

Reduced sneak path current in the proposed architecture

Enhanced conductance control accuracy using regulated sources

Potential for improved energy efficiency in neuromorphic computing

Abstract

Memristors are promising devices for scalable and low power, in-memory computing to improve the energy efficiency of a rising computational demand. The crossbar array architecture with memristors is used for vector matrix multiplication (VMM) and acts as kernels in neuromorphic computing. The analog conductance control in a memristor is achieved by applying voltage or current through it. A basic 1T1R array is suitable to avoid sneak path issues but suffer from wire resistances, which affects the read and write procedures. A conductance control scheme with a regulated voltage source will improve the architecture and reduce the possible potential divider effects. A change in conductance is also possible with the provision of a regulated current source and measuring the voltage across the memristors. A regulated 2T1R memristor conductance control architecture is proposed in this work, which avoids the potential divider effect and virtual ground scenario in a regular crossbar scheme, as well as conductance control by passing a regulated current through memristors. The sneak path current is not allowed to pass by the provision of ground potential to both terminals of memristors.