Is Semantic SLAM Ready for Embedded Systems ? A Comparative Survey

TL;DR

This paper reviews recent Semantic Visual SLAM methods, comparing their performance and resource demands on embedded hardware, highlighting the trade-offs between accuracy and efficiency for real-world robotic applications.

Contribution

It provides a comprehensive comparison of Geometric SLAM, NeRF, and Gaussian Splatting architectures on embedded hardware, emphasizing practical considerations for resource-limited systems.

Findings

NeRF and Gaussian Splatting achieve high semantic detail but are resource-intensive.

Semantic Geometric SLAM offers a better balance of accuracy and efficiency.

Current methods need better adaptation for embedded environments.

Abstract

In embedded systems, robots must perceive and interpret their environment efficiently to operate reliably in real-world conditions. Visual Semantic SLAM (Simultaneous Localization and Mapping) enhances standard SLAM by incorporating semantic information into the map, enabling more informed decision-making. However, implementing such systems on resource-limited hardware involves trade-offs between accuracy, computing efficiency, and power usage. This paper provides a comparative review of recent Semantic Visual SLAM methods with a focus on their applicability to embedded platforms. We analyze three main types of architectures - Geometric SLAM, Neural Radiance Fields (NeRF), and 3D Gaussian Splatting - and evaluate their performance on constrained hardware, specifically the NVIDIA Jetson AGX Orin. We compare their accuracy, segmentation quality, memory usage, and energy consumption. Our results show that methods based on NeRF and Gaussian Splatting achieve high semantic detail but demand substantial computing resources, limiting their use on embedded devices. In contrast, Semantic Geometric SLAM offers a more practical balance between computational cost and accuracy. The review highlights a need for SLAM algorithms that are better adapted to embedded environments, and it discusses key directions for improving their efficiency through algorithm-hardware co-design.